An effective method for the blind assembly of surface mountable semiconductor packages such as chip carriers to ceramic or epoxy-glass interconnect boards has been an elusive goal in integrated circuit packaging technology. Chip carrier designs containing closely packed conductor pads or pins must be precisely aligned during assembly to an array of conductor pads on the support or interconnection board. In many cases, however, an optical alignment of the conductor pads on the mating surfaces is difficult because they are recessed from the edge of the carrier and consequently obscured from view. Therefore, alignment schemes that use either fiducial markings or package edge registration techniques are often employed. Both of these approaches have drawbacks.